Integrated circuits and other microelectronic devices utilize signal lines for a variety of reasons. For example, signal lines are used to route logic signals. Signal lines are typically formed of metal such as aluminum or copper, although essentially any electrically conductive material such as doped polysilicon and silicide can be used. Signal lines are formed using well known techniques, such as by forming and patterning an electrically conductive layer or by selectively depositing an electrically conductive layer.
As the art moves towards higher density reduced feature size integrated circuits, the spacing between signal lines decreases. Decreasing the spacing between signal lines undesirably increases the capacitive coupling between adjacent signal lines. This capacitive coupling can degrade device performance. For example, a change in voltage on a first signal line can be capacitively coupled to an adjacent second signal line thus inducing an instantaneous voltage on the second signal line. This induced voltage may be confused as a valid logic signal causing logic errors in the integrated circuit.
To reduce or prevent capacitive coupling between signal lines, it has become known to place a shield line between adjacent signal lines. FIG. 1 is a perspective view of a structure 10 which includes a shield line 12 interposed between adjacent signal lines 14, 16 in accordance with the prior art. Shield line 12, signal lines 14, 16 are all part of a single conductor layer M1, for example, are part of the metal one layer. Typically, shield line 12, signal lines 14, 16 are on an electrically insulating layer above a semiconductor substrate.
As those skilled in the art understand, signal lines are part of various conductor layers (often referred to as metal layers) formed above one another. These conductor layers are electrically isolated from one another by electrically insulating layers such as silicon oxide layers. Electrically conductive vias electrically connect corresponding signal lines between conductor layers.
In this illustration, shield line 12 is electrically connected to a reference line 22 which is part of a conductor layer M2 (e.g. the metal two layer) by a via 20. Reference line 22, in turn, is electrically connected to a reference line 26 which is part of a conductor layer M3 (e.g. the metal three layer) by a via 24. Reference line 26 is electrically connected to a voltage source 18. For example, voltage source 18 is a reference voltage source, i.e., is ground.
Since shield line 12 is electrically connected to voltage source 18, shield line 12 is held at a common potential. Thus, induced voltages do not appear on shield line 12. As a result, signal lines 14, 16 are shielded from one another by shield line 12.
Signal lines 14, 16 and shield line 12 are typically designed using an automated routing program. As those skilled in the art understand, such routing programs operate using a point to point designation. In particular, a designer specifies the points which need connection and the routing program automatically lays out the signal lines and vias required to make the point to point connections while at the same time allocating area for the shield lines. The shield lines are then laid out in this allocated area. Thus, to form structure 10, the routing program automatically allocates a particular area (or percentage) of the total substrate surface area to accommodate shield line 12, vias 20, 24 and reference lines 22, 26. However, this undesirably increases the overall length of the signal lines as discussed in more detail with reference to FIG. 2. As used herein, the term “substrate surface area” and similar terms are used generally to represent the cumulative area of each conductor layer.
FIG. 2 is a top plan view of structure 10 of FIG. 1. As shown in FIG. 2, the routing program allocates significant area to accommodate shield line 12. In particular, an area having a width equal to a distance CD between signal line 14 and shield line 12 plus a distance FW equal to the width of shield line 12 is allocated to accommodate shield line 12. To minimize this area, the distanced CD is the minimum distance allowable between features (hereinafter referred to as critical distance CD) and the distance FW is the minimum allowable width of a feature (hereinafter referred to as the minimum feature width FW). Illustratively, critical distance CD is 0.2 μm and minimum feature width FW is also 0.2 μm although other values can be used depending upon the particular design.
The routing program also allocates a significant area to accommodate the electrical connection of shield line 12 to voltage source 18. In particular, via 20 is offset from via 24 by a via offset distance VO. This offset is required due to design rules which prevent a via from being formed directly on top of an underlying via. This offset also requires reference line 22 to be provided to electrically connect vias 20, 24. Since a similar offset is required for each conductor layer and there are several conductor layers, e.g. six or more, this offset is repeated several times and requires the allocation of a substantial area of the substrate.
Accordingly, the routing program allocates a substantial percentage of the total substrate surface area to accommodate shield line 12 and the electrical connection of shield line 12 to voltage source 18. Since the signal lines must be routed around this allocated area, the overall length of the signal lines increases. However, it is desirable to decrease the overall length of the signal lines to improve performance of the integrated circuit. Thus, the art needs a method of providing shield lines without having to allocate a percentage of the total substrate surface area for the shield line and/or for the electrical connection of the shield line to the voltage source.